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MOS 6502 and its derivates are used in Commodore 8-bit computers PET, VIC20, C64, C16, Plus/4, C128 and some other models

MOS 6502
X65 8-bit CPU
Max. clock speed:
6502/6510/8500 1MHz
6502A 2MHz
6502B 3MHz
6502C 4MHz
7501/8501 1,77MHz
8502 2MHz
CPU registers: Accumulator, X-index, Y-index, Stack Pointer, Program Counter, Status Register
16-bit address bus allowing access 64K memory directly

MOS Technology 6502 is an 8-bit microprocessor that was designed by Chuck Peddle and Bill Mensch for MOS Technology in 1975
When it was introduced, it was the least expensive full-featured CPU on the market by a considerable margin, costing less than one-sixth the price of competing designs from larger companies such as Motorola and Intel. It was nevertheless fully comparable with them, and, along with the Zilog Z80, sparked a series of computer projects that would eventually result in the home computer revolution of the 1980s. The 6502 design, with about 4000 transistors, was originally second-sourced by Rockwell and Synertek and later licensed to a number of companies; it is still made for embedded systems. MOS 6502 or 65xx family was used in some of Commodore computers as main processor, but it features also in Apple I, II and III, Atari 400, 800, 600XL, 800XL and 2600 and other computers

Technical description
MOS 6502 is an 8-bit processor with a 16-bit address bus
The internal logic runs at the same speed as the external clock rate, but despite the slow clock speeds (typically in the neighborhood of 1 or 2 MHz), the 6502's performance was actually competitive with other CPUs using significantly faster clocks. This is partly due to a simplistic state machine implemented by combinatorial (clockless) logic to a greater extent than in many other designs; the two phase clock (supplying two synchronizations per cycle) can thereby control the whole machine-cycle directly. Like most simple CPUs of the era, the dynamic NMOS 6502 chip was not sequenced by a microcode ROM but used a PLA (which occupied about 15% of the chip area) for instruction decoding and sequencing. Like most typical eight-bit microprocessors, the chip does some limited overlapping of fetching and execution.
The low clock frequency moderated the speed requirement of memory and peripherals attached to the CPU, as only about 50% of the clock cycle was available for memory access (due to the asynchronous design, this percentage varied strongly among chip versions). This was critical at a time when affordable memory had access times in the range 450-250ns. The original NMOS 6502 was minimalistically engineered and efficiently manufactured and therefore cheap - an important factor in getting design wins in the very price-sensitive game console and home computer markets

Like its precursor, the Motorola 6800 (but unlike Intel 8080 and similar microprocessors) the 6502 has very few registers. At the time the processor was designed, small bipolar memories were relatively fast, so it made sense to rely on RAM instead of wasting expensive NMOS chip area on CPU-registers.
The 6502's registers included one 8-bit accumulator register (A), two 8-bit index registers (X and Y), an 8-bit processor status register (P), an 8-bit stack pointer (S), and a 16-bit program counter (PC). The subroutine call/scratchpad stack's address space was hardwired to memory page $01, i.e. the address range $0100–$01FF (256–511). Software access to the stack was done via four implied addressing mode instructions whose functions were to push or pop (pull) the accumulator or the processor status register. The same stack was also used for subroutine calls via the JSR (Jump to Subroutine) and RTS (Return from Subroutine) instructions, and for interrupt handling.
The chip used the index and stack registers effectively with several addressing modes, including a fast "direct page" or "zero page" mode, similar to that found on the PDP-8, that accessed memory locations from address 0 to 255 with a single 8-bit address (saving the cycle normally required to fetch the high-order byte of the address) - code for the 6502 used the zero page much as code for other processors would have used registers. On some 6502-based microcomputers with an operating system, the OS would use most of zero page, leaving only a handful of locations for the user.
Addressing modes also included implied (1 byte instructions); absolute (3 bytes); indexed absolute (3 bytes); indexed zero-page (2 bytes); relative (2 bytes); accumulator (1); indirect,x and indirect,y (2); and immediate (2). Absolute mode was a general-purpose mode. Branch instructions used a signed 8-bit offset relative to the instruction after the branch; the numerical range -128..127 therefore translates to 128 bytes backward and 127 bytes forward from the instruction following the branch (which is 126 bytes backward and 129 bytes forward from the start of the branch instruction). Accumulator mode used the accumulator as an effective address, and did not need any operand data. Immediate mode used an 8-bit literal operand.
The indirect modes were useful for array processing and other looping. With the 5/6 cycle "(indirect),y" mode, the 8-bit Y register was added to a 16-bit base address in zero page, located by a single byte following the opcode. As the resulting address could be anywhere in the 16-bit memory range, the Y register was a true index register, as opposed to the 6800, which had one 16-bit address register. Incrementing the index register to walk the array byte-wise took only two additional cycles. With the less frequently used "(indirect,x)" mode the effective address for the operation was found at the zero page address formed by adding the second byte of the instruction to the contents of the X register. Using the indexed modes, the zero page effectively acted as a set of 128 additional (though very slow) address registers.
The 6502 also included a set of binary coded decimal (BCD) instructions, a feature normally implemented in software. Placing the CPU into BCD allowed numbers to be manipulated in base-10, with a set of conversion instructions to convert between base-10 and binary (base-2). For instance, with the "D" flag set, 99+1 would result in 00 and the carry flag being set. These instructions made implementing a BASIC programming language easier, removing the need to convert numbers for display in the BASIC interpreter itself. However, this feature meant other useful instructions could not be implemented due to a lack of CPU real estate, and was sometimes removed to make room for custom instructions.
A Byte magazine article once referred to the 6502 as "the original RISC processor," due to its efficient, simplistic, and nearly orthogonal instruction set (most instructions work with most addressing modes), as well as its 256 zero-page "registers". The 6502 is technically not a RISC design however, as arithmetic operations can read any memory cell (not only zero-page), and some instructions (inc, rol etc.) even modify memory contrary to the basic load/store philosophy of RISC. Furthermore, orthogonality is equally often associated with "CISC". However the 6502 performed reasonably well compared to other contemporaneous processors such as the Z80, which used a much faster clock rate, and the 6502 has been credited as being inspirational to RISC processors such as the ARM

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